1. Field of the Invention
The present invention generally relates to first in first out memories (FIFOs) and particularly relates to an adaptive FIFO memory controller for a digital video communications channel.
2. Description of the Related Art
A FIFO typically comprises a memory array in the form of a stack of addressable bytes of data. Data bytes are written into the stack at addresses specified by a write address counter or "pointer" in response to a write enable signal. Similarly, data bytes are read out of the stack from addresses indicated by a read address pointer in response to a read enable signal. The addresses indicated by the read and write address pointers are incremented by read and write clock signals respectively. The read and write addresses are thus respectively indicative of the number of bytes written to and the number of bytes read from the stack.
Because data can be read out of the stack at a different rate to which it was written, FIFOs are useful for providing data communication channels between two data processing systems of different bandwidths. In particular, FIFOs are useful for transferring data to a receiving system that may not be able to accept the data immediately because, for example, it is busy processing data already received. To maximize use of the data channel bandwidth available, data is preferably transferred to the receiving system through the FIFO in blocks or bursts. This usually involves allowing a quantity of data to accumulate in the FIFO before indicating to the receiving system that there is data to be received. The receiving system then reads the burst from the FIFO as a continuous data flow.
The flow of data through the FIFO is usually regulated by a FIFO controller. The FIFO controller generates a data transfer request signal to the receiving system when the difference between the number of data bits written to and the number of data bits read from the stack reaches a predetermined threshold or burst value. The receiving system reads the burst from the FIFO in response to the data transfer request signal.
The FIFO memory apparatus hereinbefore described is useful for transferring bursts of an uninterrupted data flow such as digitized samples of an audio signal for example. However, some data flows, such as digitized samples of video signals for example, can be punctuated by periodic synchronization codes. The synchronization codes associated with a digitized video signal separate the data corresponding to successive video lines of a digitized video image and data corresponding to successive video frames. If the number of samples in each video line is not divisible by the burst value, data representing the end of one video line may be retained in the FIFO as data representing the next video line is written to the FIFO. This may result in the retained data being overwritten. The receiving system may not therefore be able to reproduce the edge of the image. It is therefore desirable to ensure that the FIFO is emptied between successive video line transfers. Conventionally, this has been achieved by requesting data transfer whenever there is at least some data in the stack instead of waiting until enough data for a burst transfer has accumulated. However, this militates against maximizing use of the bandwidth of the data channel.